Devices Included in this Data Sheet: PIC16FA K .. You can determine the version of a data sheet by examining its literature number found on the. IC datasheet. PIC16FA datasheet specifies that this CMOS FLASH-based 8-bit microcontroller packs Microchip’s powerful PIC architecture into an or pin package and is upwards compatible with the PIC16C5X, PIC12CXXX and PIC16C7X devices. download PIC16FA datasheet. Learn about PIC16FA PIC series microcontroller with its a detailed overview of PIC16FA features with its PDF datasheet to download.
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Microcontrollers. PDF created with pdfFactory trial version raudone.info . PIC16FA K. .. To obtain the most uputoudate version of this data sheet, please register at our Worldwide Web site at. PIC16FA datasheet, PIC16FA circuit, PIC16FA data sheet: MICROCHIP - 28/pin Enhanced FLASH Microcontrollers,alldatasheet, datasheet. PIC16F Datasheet PDF Download - PIC16F87X 28/Pin 8-Bit CMOS FLASH Microcontrollers Devices Included in this Data Sheet: • PIC16F
PORTB can be software programmed for internal weak pull-ups on all inputs. INT I External interrupt. AN2 I Analog input 2. PORTB can be software programmed for internal weak pull-up on all inputs. AN5 I Analog input 5.
AN6 I Analog input 6. AN7 I Analog input 7. These pins 28, 40 33, 34 should be left unconnected. The program memory and data counter capable of addressing an 8K word x 14 bit memory have separate buses so that concurrent program memory space. Accessing a location above the physically implemented address will cause a Additional information on device memory may be found wraparound.
The Reset vector is at h and the interrupt vector is at h. Stack Level 8 Stack Level 8. Reset Vector h Reset Vector h. The lower locations of each bank are reserved for the Special The data memory is partitioned into multiple banks Function Registers. Function Registers. Some frequently used Special Function Registers from one bank may be mirrored in another bank for code reduction and quicker access.
RP0 Bank 00 0 Note: Indirect addr. Note 1: These registers are reserved; maintain these registers clear. Those registers The Special Function Registers are registers used by associated with the core functions are described in the CPU and peripheral modules for controlling the detail in this section. Those related to the operation of desired operation of the device. These registers are the peripheral features are described in detail in the implemented as static RAM. A list of these registers is peripheral features section.
The upper byte of the program counter is not directly accessible. These registers can be addressed from any bank. ALU, the Reset status and the bank select bits for data memory. For other ister is the destination for an instruction that affects the instructions not affecting any status bits, see Z, DC or C bits, then the write to these three bits is dis- Section These bits are set or cleared according to the device logic.
The C and DC bits operate as a borrow writable, therefore, the result of an instruction with the and digit borrow bit, respectively, in sub- Status register as destination may be different than traction. For borrow, the polarity is reversed.
To achieve a 1: RB4 pins changed state; a mismatch condition will continue to set the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared must be cleared in software. RB4 pins have changed state. Interrupt flag bits are set when an interrupt The PIR1 register contains the individual flag bits for condition occurs regardless of the state of its the peripheral interrupts.
User software should ensure the appropriate interrupt bits are clear prior to enabling an interrupt. The conditions that will set this bit are: Unused in this mode.
Interrupt flag bits are set when an interrupt The PIR2 register contains the flag bits for the CCP2 condition occurs regardless of the state of interrupt, the SSP bus collision interrupt, EEPROM its corresponding enable bit or the global write operation interrupt and the comparator interrupt. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. BOR is unknown on Power-on Reset. The low overflow or stack underflow conditions.
Figure shows the two situations or the vectoring to an interrupt address. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push.
The tenth push overwrites the second push and so on. The INDF register is not a physical register. Direct Addressing Indirect Addressing. When VDD range. This memory is not directly mapped in the selecting a data address value, only the LSByte of the register file space. When select- through the Special Function Registers. EECON1 is the control register for memory accesses.
When clear, as it is 00h to FFh. On devices with bytes, addresses from when reset, any subsequent operations will operate on 80h to FFh are unimplemented and will wraparound to the data memory. When writing operations will operate on the program memory.
Control bits, RD and WR, initiate read and write or erase, respectively. These bits cannot be cleared, only When interfacing the program memory block, the set, in software. These devices have 4 or 8K words of The WREN bit, when set, will allow a write or erase program Flash, with an address range from h to operation. On power-up, the WREN bit is clear. In these situations, following beginning of program memory.
The Flash program memory allows single-word reads and four-word block writes. Program memory Interrupt flag bit, EEIF in the PIR2 register, is set when write operations automatically perform an erase-before- the write is complete.
It must be cleared in software. The write time is controlled by an on-chip timer. The Note: On charge pump, rated to operate over the voltage range previous PIC16F87X devices, Flash pro- of the device for byte or word operations. See Section 3. When code-protected, the device programmer can no longer access data or program memory; this does NOT inhibit internal reads or writes.
The bit is cleared by hardware once write is complete. The WR bit can only be set not cleared in software. The RD bit can only be set not cleared in software. To read a data memory location, the user must write the 1.
The data is available in the very next address is not larger than the memory size of cycle in the EEDATA register; therefore, it can be read the device.
Write the 8-bit data value to be programmed in hold this value until another read or until it is written to the EEDATA register. Make sure that the 5. Set the WREN bit to enable program operations. Disable interrupts if enabled.
Execute the special five instruction sequence: Set the RD bit to start the read operation. Enable interrupts if using interrupts. WREN bit will not affect this write cycle. The user can either enable this interrupt or poll this bit.
EEIF must be cleared by software. Once the read read or until it is written to by the user during a write control bit is set, the program memory Flash controller operation.
This causes these two instructions immediately follow-. WRT0 of executed: Flash program memory must be written in four-word blocks. At the same time, all block writes to 3. The write operation is edge-aligned and cannot The user must follow the same specific sequence to ini- occur across boundaries.
After the address and data have been set up, registers are written into the program memory. Since data is being written to buffer registers, programming sequence.
The processor will halt internal operations for the typical 4 ms, only during the cycle in All four buffer register locations MUST be written to with which the erase takes place i. If only one, two or three words are being four-word block. This is not Sleep mode as the clocks written to in the block of four words, then a read from and peripherals will continue to run.
After the write the program memory location s not being written to cycle, the processor will resume operation with the third must be performed. Then the sequence of is ignored. EEADR register pair; the four words of data are loaded using indirect addressing. ADDRL ; 2. On power-up, WREN is cleared. External write access to the program memory Also, the Power-up Timer 72 ms duration prevents an is also disabled.
When program memory is code-protected, the microcon- The write initiate sequence and the WREN bit together troller can read and write to program memory normally, help prevent an accidental write during brown-out, as well as execute instructions.
Writes by the device may power glitch or software malfunction. WR0 of the configuration word see Section External access to the memory is also disabled. High-Impedance mode. All Data Data Latch write operations are read-modify-write operations.
Buffer Q D The comparators are in the off digital state. Output is open-drain type. The corre- interrupt in the following manner: This will end the pin an input i. Debugger and Low-Voltage Programming function: The alternate wake-up on key depression operation and operations functions of these pins are described in Section A using the interrupt-on-change feature. The ware configurable pull-ups on these four pins, allow weak pull-up is automatically turned off when the port easy interface to a keypad and make it possible for pin is configured as an output.
The pull-ups are wake-up on key depression. Refer to the application disabled on a Power-on Reset. EN Q1 2: Only pins configured as inputs can RB7: RB4 pins EN cause this interrupt to occur i. RB4 pin Q3 configured as an output is excluded from the interrupt- RB7: RB6 on-change comparison. The input pins of RB7: RB4 2: Internal software programmable weak pull-up.
Serial programming clock. Serial programming data. This buffer is a Schmitt Trigger input when used in Serial Programming mode or in-circuit debugger. Each pin is individually configurable as an input Port CK or output.
These pins have Schmitt Trigger CK input buffers. The user must make sure to keep the pins configured as inputs when using them as analog inputs. There are actually two 8-bit latches: Shaded cells are not used by the Parallel Slave Port. Clearing bit T0SE selects the ris- ing edge. The Figure is a block diagram of the Timer0 module and prescaler is not readable or writable. Section 5. Bit prescaler. PS0 PSA. WDT Time-out. This prescaler is not readable or writable see Figure The synchronization determine the prescaler assignment and prescale ratio.
Therefore, it is writing to the TMR0 register e. Refer to the electrical along with the Watchdog Timer. The prescaler is not specification of the desired device.
Writing to TMR0 when the prescaler is 5. A prescaler assignment for the. This sequence must be followed even if the WDT is disabled. Shaded cells are not used by Timer0. This interrupt can be Section 8. Manual DS This bit is ignored. After Timer1 is enabled in Counter mode, the module must first have a falling edge before the counter begins to increment.
The synchro- nization is done after the prescaler stage. In prescaler stage is an asynchronous ripple counter. This eliminates power drain. C1 C2 clock input is not synchronized. However, special precautions in These values are for design guidance only.
Crystals Tested: In Asynchronous Counter mode, Timer1 cannot be Higher capacitance increases the stability Reading TMR1H or TMR1L while the timer is running of oscillator but also increases the start-up from an external asynchronous clock will ensure a valid time.
However, the user 2: A write conten- tion may occur by writing to the timer registers while the 6. This may produce an unpredictable value in the timer register. Trigger Output Reading the bit value requires some care. Asynchronous mode. It is enabled by nized Counter mode to take advantage of this feature. The oscil- If Timer1 is running in Asynchronous Counter mode, lator is a low-power oscillator, rated up to kHz.
It this Reset operation may not work. It is primarily intended In the event that a write to Timer1 coincides with a for use with a 32 kHz crystal.
The Timer1 oscillator is identical to the LP oscillator. CCPRxL regis- The user must provide a software time delay to ensure ter pair effectively becomes the period register for proper oscillator start-up. In all other Resets, the register is unaffected. Shaded cells are not used by the Timer1 module. The TMR2 register is readable and writable and is cleared on any device Reset. TMR2 Reg 1: PR2 is Postscaler 2 Comparator 1: SSP module as a baud clock.
Shaded cells are not used by the Timer2 module. The special event trigger is generated by a compare match and will reset Timer1. Compare mode: PWM mode: An event is defined as one of the capture feature.
In Asynchronous Counter mode, the following: When a cap- change in operating mode. The interrupt flag must be cleared in 8. Whenever the CCP module is overwritten by the new value. Any Reset will clear 8.
Also, the prescaler counter will not be cleared, therefore, the first capture may be from Note: Example shows the recom- output, a write to the port can cause a mended method for switching between capture Capture condition.
In Asynchronous Counter mode, the compare operation may not work. At the a CCP interrupt if enabled. TMR1 register pair. R Match. Since register. The Timer2 postscaler see Section 7. CCPR1L 8. In PWM mode, Note 1: This A PWM output Figure has a time base period double-buffering is essential for glitch-free PWM and a time that the output stays high duty cycle. The operation. Shaded cells are not used by Capture and Timer1.
The PSP is not implemented on pin devices; always maintain these bits clear.
Shaded cells are not used by PWM and Timer2. SSPM0 9. Additional details are provided under the individual sections. The transmitted and received simultaneously. These are: Sample bit SPI Master mode: Stop bit Used in I2C mode only.
Start bit Used in I2C mode only.
Update Address bit Used in I2C mode only. Must be cleared in software. Overflow can only occur in Slave mode. When enabled, these pins must be properly configured as input or output. SS pin control disabled. SS pin control enabled.
Bit combinations not specifically listed here are either reserved or implemented in I2C mode only. User software must clear specified. The not occur. This double-buffering of the received data SSPBUF allows the next byte to start reception before reading the data that was just received. Any write to the. To reset or reconfigure microcontrollers.
For the pins to behave as the serial port func- edge of the clock.
PIC16F877A PDF – Microcontrollers – Microchip
Both processors should be tion, some must have their data direction bits in the programmed to the same Clock Polarity CKP , then TRIS register appropriately programmed. That is: Whether the data is meaningful or dummy data depends on the application software.
Any serial port function that is not desired may be overridden by programming the corresponding data direction TRIS register to the opposite value. In Master mode, the SPI clock rate The master can initiate the data transfer at any time bit rate is user programmable to be one of the because it controls the SCK. The master determines following: SDI pin at the programmed clock rate. This could be useful in receiver there is a clock edge on SCK.
This then, would give waveforms for SPI communication as shown in. When the may be desirable, depending on the application. While in Slave mode, the external clock is supplied by Note 1: When a byte is received, the device will wake-up set, then the SS pin control must be from Sleep.
When the SPI module resets, the bit counter is forced 9. The SS pin allows a Synchronous Slave mode. The pin must not be driven low operate as a receiver, the SDO pin can be configured for the SS pin to function as an input. The data latch as an input. This disables transmissions from the SDO. When since it cannot create a bus conflict. SDO bit 7 bit 6 bit 7 bit 0. After the device returns to CKE control bits. In Slave mode: In Master mode: Buffer Full Status bit In Transmit mode: Receive Overflow Indicator bit In Receive mode: Used to ensure data setup time.
Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. Automatically cleared by hardware.
All incom- tion. SCL line. The Buffer Full bit, BF, is set. Stop bit interrupts enabled 3. An ACK pulse is generated. To ensure proper operation MSbs of the first address byte specify if this is a bit of the module, pull-up resistors must be provided address. For a bit address, the first byte would equal 9.
The MSSP module bit address is as follows, with steps 7 through 9 for will override the input state with the output data when the slave-transmitter: Through the mode 2.
When an address is matched, or the data transfer after 3. Receive Repeated Start condition. The 9. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter and parameter An overflow more detail.
See Section 9. An MSSP interrupt is generated for each data transfer byte. ACK is not sent. By holding the SCL line 9. By holding 2: This will prevent buffer overruns from occurring see Transmit Mode Figure In bit Slave Transmit mode, clock stretching is con- trolled during the first two address sequences by the Note 1: After stretching will not occur.
The CKP bit can be set in software not set, the module is now configured in Transmit regardless of the state of the BF bit.
The mode and clock stretching is controlled by the BF flag user should be careful to clear the BF bit as in 7-bit Slave Transmit mode see Figure During this time, if the UA bit is set after the ninth clock, clock stretching is initiated.
Microchip Tech PIC16F877A-I/P
Clock stretching will occur on each data receive sequence as described in 7-bit mode. Clock stretching, on the basis of the state of the BF bit, only occurs during a data sequence, not an address sequence.
Master device asserts clock CKP. When the interrupt is serviced, the source for the inter- The exception is the general call address which can rupt can be checked by reading the contents of the address all devices. The value can be used to determine if the devices should, in theory, respond with an Acknowledge. Following a Start bit detect, 8 bits are shifted into be set and the slave will begin receiving data after the the SSPSR and the address is compared against the Acknowledge Figure It is also compared to the general call address and fixed in hardware.
Address is compared to general call address. After ACK, set interrupt. Configure the I2C port to receive data.
PIC16F877A Datasheet PDF – Microcontroller – Microchip
DSC-page 1. This document contains device specific information. All devices in the. The available features are summarized in Table The pinouts for these. Range Reference Manual DS , which may be. The Refer-. TABLE Key Features. Operating Frequency. Resets and Delays. Flash Program Memory. Data Memory bytes. Serial Communications. DC — 20 MHz. Ports A, B, C. External data memory is not directly addressable except in some PIC18 devices with high pin count.
In general, there is no provision for storing code in external memory due to the lack of an external memory interface. However, the unit of addressability of the code space is not generally the same as the data space. In contrast, in the PIC18 series, the program memory is addressed in 8-bit increments bytes , which differs from the instruction width of 16 bits.
In order to be clear, the program memory capacity is usually stated in number of single-word instructions, rather than in bytes. Stacks[ edit ] PICs have a hardware call stack , which is used to save return addresses. The hardware stack is not software-accessible on earlier devices, but this changed with the 18 series devices. Hardware support for a general-purpose parameter stack was lacking in early series, but this greatly improved in the 18 series, making the 18 series architecture more friendly to high-level language compilers.
The instruction set includes instructions to perform a variety of operations on registers directly, the accumulator and a literal constant or the accumulator and a register , as well as for conditional execution, and program branching.
Some operations, such as bit setting and testing, can be performed on any numbered register, but bi-operand arithmetic operations always involve W the accumulator , writing the result back to either W or the other operand register.
To load a constant, it is necessary to load it into W before it can be moved into another register. On the older cores, all register moves needed to pass through W, but this changed on the "high-end" cores.
PIC cores have skip instructions, which are used for conditional execution and branching. The skip instructions are "skip if bit set" and "skip if bit not set". Because cores before PIC18 had only unconditional branch instructions, conditional jumps are implemented by a conditional skip with the opposite condition followed by an unconditional branch.
Skips are also of utility for conditional execution of any immediate single following instruction. It is possible to skip instructions. The 18 series implemented shadow registers, registers which save several important registers during an interrupt, providing hardware support for automatically saving processor state when servicing interrupts.The bit is cleared by hardware once write is complete.
See Interrupt Sources.
Interrupt flag bits are set when an interrupt The PIR1 register contains the individual flag bits for condition occurs regardless of the state of its the peripheral interrupts. Address is compared to general call address. The MSSP module bit address is as follows, with steps 7 through 9 for will override the input state with the output data when the slave-transmitter: